- Cadence tool helps Nvidia model Rubin GPU power demands across billions of cycles
- Early analysis will help Nvidia improve chip efficiency and power consumption levels
- Nvidia and AMD hardware both contribute to Cadence emulation and prototyping platform
Cadence Design Systems has created a Dynamic Power Analysis tool designed to handle very large chip designs, including Nvidia’s Rubin GPU which carries more than 40 billion gates.
eeNews Europe reports the software operates on the Palladium Z3 emulator, allowing engineers to examine with incredibly high accuracy how energy is consumed across billions of cycles in only a few hours.
This is especially useful for AI accelerators like Rubin, where workloads vary widely and can stress different areas of the design at different times.
Addressing early bottlenecks
Power modelling is increasingly important as chips grow larger and energy demands rise.
Rubin could draw around 700W for a single die, with multi-chip configurations consuming up to 3.6kW. By running early simulations, design teams can size networks more accurately, spotting and addressing bottlenecks before the chip even reaches production.
eeNews says Rubin has been reported to require a respin. It taped out with TSMC in June on its 3nm N3P process, but Nvidia is looking to further boost performance in preparation for a battle against AMD’s upcoming MI450.
This could delay the first Rubin samples into 2026, although shipments are still expected to begin towards the end of that year.
The Cadence DPA app will play a central role in navigating these challenges, eeNews says. The emulator can reportedly handle up to 48 billion gates, supporting chip-level estimation of peaks and averages in power draw.
This enables developers to balance performance with efficiency while also limiting risks of delay from underpowered or oversized networks.
The Palladium Z3 platform itself uses Nvidia’s BlueField data processing unit and Quantum Infiniband networking to connect with the Protium X3 FPGA prototyping system.
The Protium platform is based on AMD Ultrascale FPGAs, which can run RTL models of designs, enabling early software testing before silicon is available. In this way, both Nvidia and AMD hardware are involved in supporting Rubin’s design cycle.
Cadence first introduced a DPA app in 2016, but the rising complexity of AI processors has since made such tools essential.
In Rubin’s case, the analysis and prototyping platforms will help engineers manage power demands at a scale not seen before, and the lessons learned here are expected to filter down into consumer products as the technology matures.
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