Racing to scale AI requires massive capital investment in data centers, with McKinsey recently estimating that global data center spending could reach $7 trillion by 2030. Perhaps more importantly, though, scaling AI requires massive architectural investment from a technology standpoint.
Modern data center infrastructure was not designed to power the cloud computing revolution and the massive surge in AI usage and development on a global scale simultaneously.
Executive Vice-President, Chief Product Officer at Soitec.
This architectural strain is driven by rising expectations – the more AI is adopted, the more demand of it there is. Enterprises are excited by AI’s promise as a time-saver that can automate and streamline employee workflows and increase productivity. To facilitate the growing complexity of AI models and datasets, GPU density and bandwidth have increased in data centers.
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These increases mean AI models that can be trained faster, have lower latency interference and more. As these chips and data centers continue to increase the amount of data transferred between chips, though, cooling efforts are also needed to make sure the chips and data centers do not overheat.
As a result, while today’s data centers continue to power the AI boom, their operational runway is quickly shortening. Powering AI and the growing demand for AI capabilities is incredibly resource intensive. The technology relies heavily on electrons for computational capabilities and for moving data between chips in larger AI models. This requires vast amounts of electricity, water, rare materials, and overall technological innovation.
As operational bottlenecks persist, silicon photonics has proven an underappreciated solution to help further advance AI. Using light combination with electrons, silicon photonics enables faster, more energy-efficient data transmission. These abilities can both advance AI and scale GPU clusters and AI data centers.
The SiPh adoption delay
Photonics have been around for decades, spanning more than 40 years of research and innovation. In the 1980s, researchers realized the technology’s potential due to its ability to allow the integration of photonics and electronics on a single chip.
Where before, photonic and electronic components lived on two separate chips that had to be combined, silicon photonics made it possible for both components to be functional on one single chip, resulting in increased speed, bandwidth, energy efficiency and more.
Today, silicon photonics are integral to the commercial production of communications transceivers in data centers. Fiber-optic communication predates the current AI wave by an entire generation, as does the basic principle of transmitting data as light rather than an electrical current.
The challenge of leveraging this technology in a broader setting, however, has always been its manufacturability and the need for optical components to be small and cheap enough to compete with legacy conventional solutions.
Complementary metal-oxide-semiconductor (CMOS) compatibility makes this possible.
CMOS
Silicon Photonics-based circuits converts electrical signals into optical ones, transmits them as infrared light pulses through microscopic waveguides etched into silicon, and converts them back to electrical signals at the destination.
CMOS platform unlocks efficient and high-scale integration of passive and active devices onto Photonics Integrated Circuits (PICs), used to make optical transceivers. The physics of light propagation delivers far lower loss than copper interconnects do at the data rates modern AI workloads demand.
With CMOS, silicon photonics can be fabricated using the same processes semiconductor fabs use for conventional chips. This process allows optical and electronic components to coexist on a single silicon die, with limited use of rare materials or separate production lines, enabling scalable production.
Discussions of silicon photonics tend to focus on the transceiver or circuit design. While these conversations are essential, the substrate is equally important, delivering bandwidth and energy efficiency. Leveraging substrates to help meet growing data demands has been shown to decrease energy consumption by 30-50% on average.
Engineered substrates are silicon-on-insulator (SOI) platforms designed for photonic or high-frequency applications that support a range of markets, including mobile communications, edge AI, cloud AI, Internet of Things and data centers. With the latter, there are a variety of engineered substrates that improve different performance metrics, including Photonics-SOI, PD-SOI and RF-SOI.
Substrate selection is foundational to silicon photonics performance, not incidental to it. The choices made early in the design process determine whether a photonic chip delivers its theoretical efficiency and performance or falls short in deployment.
Scaling data centers requires scaling silicon photonics—now
The semiconductor industry must accelerate silicon photonics production to keep pace with the growth of demand for tomorrow’s data centers.
The technology works. The physics is proven. The manufacturing pathway exists. What’s missing is widespread industry alignment and investment to produce silicon photonics at the pace AI infrastructure will require.
Coordinated investment in silicon photonics must happen across chipmakers, substrate suppliers, packaging specialists, and hyperscalers whose data centers will ultimately run on this technology. That coordination is currently happening in pockets, and it needs to be prioritized — the AI buildout is not slowing down.
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