- AMD’s MI400 APU lands in 2026, boosting AI, HPC, and compute efficiency
- New design features two AIDs with eight XCDs, doubling MI300’s density
- Multimedia IO Die offloads IO tasks and may integrate Xilinx FPGA tech
AMD’s Instinct MI400 APU is set to arrive in 2026 – designed for AI, machine learning, and HPC workloads, the MI400 will build on Team Red’s chiplet-based modular architecture and is expected to increase compute density, power efficiency, and scalability.
It may also play a role in future supercomputing projects, including a possible successor to El Capitan, but so far, AMD has only confirmed that the MI400 will use the CDNA “Next” architecture.
However,ut a patch updating the API header for MES (MicroEngine Scheduler) v12, spotted by Coelacanth’s Dream (and reported by VideoCardz), provides some insight into its chiplet configuration.
According to the patch, the MI400 will feature two Active Interposer Dies (AIDs), each containing four Accelerated Compute Dies (XCDs), for a total of eight XCDs. This doubles the XCD count per AID compared to the MI300. By integrating more compute dies into fewer interposers, AMD could reduce latency and improve efficiency while increasing data throughput, which is critical for AI and HPC workloads.
However, as Coelacanth’s Dream points out, “if the MI400 follows a similar CPU Complex Die (CCD) and AID partitioning as the MI300, where some AIDs are dedicated to CPUs rather than accelerators, then the maximum number of XCDs in some configurations could be limited to four, potentially reducing the XCD count compared to the MI300A APU.”
An intriguing addition to the MI400 is the Multimedia IO Die (MID), which separates the multimedia engine from the AIDs. The MID will likely manage memory controllers, media engines, and interface logic, allowing the compute dies to focus on processing tasks. The patches suggest support for up to two MIDs, probably assigning one per AID.
This new component could be AMD’s first integration of Versal/Xilinx FPGA technology into its accelerator lineup. AMD announced in 2022 that it planned to incorporate Xilinx’s FPGA-powered AI inference engine into its CPU portfolio. It could also be an Alveo series data center acceleration card.
The patches additionally reference a Register Remapping Table (RRMT), allowing firmware to direct register transactions to specific AIDs, XCDs, or MIDs.
AMD has not yet released any official renders or specifications for the MI400 series, but with the accelerator expected to launch in 2026, following the arrival of the Instinct MI350 series (built on the CDNA 4 architecture) later this year, more details will hopefully emerge soon.
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waynewilliams@onmail.com (Wayne Williams)
