JEDEC’s SPHBM4 plan shifts HBM economics toward cheaper substrates without changing who actually gets to use it today




  • SPHBM4 cuts pin counts dramatically while preserving hyperscale-class bandwidth performance
  • Organic substrates reduce packaging costs and relax routing constraints in HBM designs
  • Serialization shifts complexity into signaling and base logic silicon layers

High bandwidth memory has evolved around extremely wide parallel interfaces, and that design choice has defined both performance and cost constraints.

HBM3 uses 1024 pins, a figure that already pushes the limits of dense silicon interposers and advanced packaging.


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