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    XCENA’s MX1 computational memory combines thousands of RISC-V cores with CXL 3.2 and SSD tiering




    • XCENA introduced MX1 computational memory with thousands of RISC-V cores at FMS 2025
    • MX1 offers near-data processing reducing CPU-memory overhead and enabling petabyte-scale SSD backed expansion
    • Product roadmap includes MX1P this year and MX1S in 2026 supporting CXL 3.2

    At the recent FMS 2025 event (formerly Flash Memory Summit but now called Future of Memory and Storage to better suit its expanded focus), South Korean startup XCENA took the wraps off its first product, MX1 Computational Memory.

    MX1 is built on the PCIe Gen6 and the Compute Express Link 3.2 standard. In putting compute directly next to DRAM, the chip is able to reduce the overhead of moving data back and forth between processors and memory.

    https://cdn.mos.cms.futurecdn.net/dHJLxqoQLn6phMf6FuPmvY.jpg



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    waynewilliams@onmail.com (Wayne Williams)

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